Getting Started with CV32E40P

This page discusses initial steps and requirements to start using CV32E40P in your design.

Register File

CV32E40P comes with two different register file implementations. Depending on the target technology, either the implementation in or the one in should be selected in the manifest file. For more information about the two register file implementations and their trade-offs, check out Register File.

Clock Gating Cell

CV32E40P requires clock gating cells. These cells are usually specific to the selected target technology and thus not provided as part of the RTL design. A simulation-only version of the clock gating cell is provided in This file contains a module called cv32e40p_clock_gate that has the following ports:

  • clk_i: Clock Input

  • en_i: Clock Enable Input

  • scan_cg_en_i: Scan Clock Gate Enable Input (activates the clock even though en_i is not set)

  • clk_o: Gated Clock Output

Inside CV32E40P, clock gating cells are used both in and For more information on the expected behavior of the clock gating cell when using the latch-based register file check out Register File.

The file is not intended for synthesis. For ASIC synthesis and FPGA synthesis the manifest should be adapted to use a customer specific file that implements the cv32e40p_clock_gate module using design primitives that are appropriate for the intended synthesis target technology.